Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias

Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene been shown to possess better performance reliability with respect dual-damascene (DD) SE-enabled wires, multi-level interconnect (with vias) has remained elusive, which is of paramount importance its in future nodes. This work, first time, addresses that need by engineering CMOS-compatible solid-phase growth technique yield large-area multilayer (MLG) on dielectric (SiO 2 ) (Cu) substrates subsequently demonstrating MLG vias. Using rigorous theoretical experimental analyses, we demonstrate vias undergo <; 2% change via under accelerated stress conditions, superior against SH EM, making them ideal candidates sub-10 nm